The subject invention is related to instruction prefetch buffers for microprocessors and, more particularly, to a register selection mechanism which enables instruction access on instruction boundaries when used with a microprocessor that operates with variable length instructions.
Single chip integrated circuit (IC) icroprocessors are of course well known in the art. These devices have been developed over the past decade from the relatively simple to the very complex. Early examples were limited to 4-bit devices while currently 32-bit devices are being introduced by various manufacturers. Along with an increase in scale, there has been a corresponding increase in sophistication of design to permit greater flexibility in programming. In one specific example, a microprocessor has been developed which operates with variable length instructions. These instructions may be either 32 bits in length or 16 bits in length. It is necessary in order to properly decode the operation codes and operands of the instruction fields that they be accessed on their boundaries. In a specific implementation of the microprocessor, the instruction prefetch buffer comprises four registers. The organization of these registers requires eight inputs to the multiplexers used for the extraction of the operation codes and the operand fields. Because of the lack of space on the microprocessor chip, it is not possible to implement a larger size instruction prefetch buffer because of the number of multiplexer inputs and the overhead required for the wiring.